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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 5 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ICCAD
2005
IEEE
125views Hardware» more  ICCAD 2005»
14 years 5 months ago
Robust mixed-size placement under tight white-space constraints
A novel and very simple correct-by-construction top-down methodology for high-utilization mixed-size placement is presented. The PolarBear algorithm combines recursive cutsize-dri...
Jason Cong, Michail Romesis, Joseph R. Shinnerl
ICCAD
2004
IEEE
102views Hardware» more  ICCAD 2004»
14 years 5 months ago
True crosstalk aware incremental placement with noise map
Crosstalk noise has become an important issue as technology scales down for timing and signal integrity closure. Existing works to fix crosstalk noise are mostly done at the rout...
Haoxing Ren, David Zhigang Pan, Paul Villarrubia
ICCAD
2004
IEEE
128views Hardware» more  ICCAD 2004»
14 years 5 months ago
Power estimation for cycle-accurate functional descriptions of hardware
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...
ICCAD
2003
IEEE
148views Hardware» more  ICCAD 2003»
14 years 5 months ago
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both th...
Navaratnasothie Selvakkumaran, George Karypis