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GECCO
2007
Springer
169views Optimization» more  GECCO 2007»
14 years 2 months ago
An evolutionary platform for developing next-generation electronic circuits
In this paper, a new method for evolving simple electronic circuits is discussed, with the aim of improving the reliability and performance of basic circuit blocks. Next-generatio...
James A. Hilder, Andy M. Tyrrell
CHINAF
2006
110views more  CHINAF 2006»
13 years 7 months ago
Time-domain analysis methodology for large-scale RLC circuits and its applications
: With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical d...
Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong ...
DAC
2002
ACM
14 years 8 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
FCCM
2004
IEEE
101views VLSI» more  FCCM 2004»
13 years 11 months ago
Secure Remote Control of Field-programmable Network Devices
A circuit and an associated lightweight protocol have been developed to secure communication between a control console and remote programmable network devices1 . The circuit provi...
Haoyu Song, Jing Lu, John W. Lockwood, James Mosco...
ICCAD
1995
IEEE
163views Hardware» more  ICCAD 1995»
13 years 11 months ago
Signal integrity optimization on the pad assignment for high-speed VLSI design
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
Kai-Yuan Chao, D. F. Wong