1476 search results - page 69 / 296 » Three-dimensional integrated circuits |
DAC
2005
ACM
13 years 11 months ago
2005
ACM
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and perfor...
GLVLSI
2010
IEEE
14 years 2 months ago
2010
IEEE
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the in...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
As research begins to explore potential nanotechnologies for future post-CMOS integrated systems, modeling and simulation environments must be developed that can accommodate the c...
TCAD
2002
13 years 8 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...