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» Throughput optimization of general non-linear computations
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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 16 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
MOBICOM
2010
ACM
13 years 7 months ago
Intentional networking: opportunistic exploitation of mobile network diversity
Mobile devices face a diverse and dynamic set of networking options. Using those options to the fullest requires knowledge of application intent. This paper describes Intentional ...
Brett D. Higgins, Azarias Reda, Timur Alperovich, ...
DAC
2002
ACM
14 years 8 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou
VEE
2009
ACM
171views Virtualization» more  VEE 2009»
14 years 2 months ago
Dynamic memory balancing for virtual machines
Virtualization essentially enables multiple operating systems and applications to run on one physical computer by multiplexing hardware resources. A key motivation for applying vi...
Weiming Zhao, Zhenlin Wang
IWCMC
2006
ACM
14 years 1 months ago
A joint technical and micro-economic investigation of pricing data services over wireless LANs
In this paper, we analyze a wireless LAN hot-spot, based on the IEEE 802.11b protocol, and more specifically we address the issue of defining proper pricing strategies, from bot...
Leonardo Badia, Federico Rodaro, Michele Zorzi