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» Throughput-centric routing algorithm design
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137
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ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 9 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
GLVLSI
2007
IEEE
328views VLSI» more  GLVLSI 2007»
15 years 10 months ago
New timing and routability driven placement algorithms for FPGA synthesis
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...
125
Voted
ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
16 years 16 days ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
148
Voted
MOBICOM
2003
ACM
15 years 9 months ago
Minimum energy disjoint path routing in wireless ad-hoc networks
We develop algorithms for finding minimum energy disjoint paths in an all-wireless network, for both the node and linkdisjoint cases. Our major results include a novel polynomial...
Anand Srinivas, Eytan Modiano
126
Voted
FOCS
2006
IEEE
15 years 9 months ago
Improved Bounds for Online Routing and Packing Via a Primal-Dual Approach
In this work we study a wide range of online and offline routing and packing problems with various objectives. We provide a unified approach, based on a clean primal-dual method...
Niv Buchbinder, Joseph Naor