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CP
2010
Springer
13 years 6 months ago
Testing Expressibility Is Hard
We study the expressibility problem: given a finite constraint language Γ on a finite domain and another relation R, can Γ express R? We prove, by an explicit family of example...
Ross Willard
ICPP
2002
IEEE
14 years 9 days ago
Analysis of Memory Hierarchy Performance of Block Data Layout
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In...
Neungsoo Park, Bo Hong, Viktor K. Prasanna
CHI
2007
ACM
14 years 7 months ago
Content-aware layout
We describe content-aware layout (CAL), a technique that automatically arranges windows on a user's desktop. Unlike conventional window managers that automatically cascade or...
Edward W. Ishak, Steven Feiner
FPGA
2005
ACM
215views FPGA» more  FPGA 2005»
14 years 26 days ago
Design, layout and verification of an FPGA using automated tools
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
Ian Kuon, Aaron Egier, Jonathan Rose
DATE
2004
IEEE
103views Hardware» more  DATE 2004»
13 years 11 months ago
A Novel Implementation of Tile-Based Address Mapping
Tile-based data layout has been applied to achieve various objectives such as minimizing cache conflicts and memory row switching activity. In some applications of tilebased mappi...
Sambuddhi Hettiaratchi, Peter Y. K. Cheung