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ICCAD
1997
IEEE
117views Hardware» more  ICCAD 1997»
14 years 2 months ago
Decomposition of timed decision tables and its use in presynthesis optimizations
Presynthesis optimizations transform a behavioral HDL description into an optimized HDL description that results in improved synthesis results. In this paper we introduce the decom...
Jian Li, Rajesh K. Gupta
ACSD
2009
IEEE
87views Hardware» more  ACSD 2009»
14 years 2 months ago
Saving Space in a Time Efficient Simulation Algorithm
A number of algorithms are available for computing the simulation relation on Kripke structures and on labelled transition systems representing concurrent systems. Among them, the...
Silvia Crafa, Francesco Ranzato, Francesco Tapparo
FCCM
2007
IEEE
168views VLSI» more  FCCM 2007»
13 years 10 months ago
Discrete-Time Cellular Neural Networks in FPGA
This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions o...
J. Javier Martínez-Álvarez, F. Javie...
ICCAD
2009
IEEE
126views Hardware» more  ICCAD 2009»
13 years 8 months ago
Timing Arc based logic analysis for false noise reduction
The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it ...
Murthy Palla, Jens Bargfrede, Stephan Eggersgl&uum...
ARCS
2004
Springer
14 years 2 months ago
Evaluation of Run-Time Reconfiguration for General-Purpose Computing
: In order to investigate the impact of dynamic hardware reconfiguration on general-purpose applications, we present a superscalar micro-architecture that includes a variable numbe...
Adronis Niyonkuru, Hans Christoph Zeidler