6111 search results - page 52 / 1223 » Time, Hardware, and Uniformity |
MSS
2011
IEEE
13 years 2 months ago
2011
IEEE
ISQED
2007
IEEE
14 years 2 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
ASPDAC
1999
ACM
14 years 1 days ago
1999
ACM
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Compared with a single level Hamming associative memory, a simple model based on uniform random noise analysis has proved a twolevel decoupled Hamming network to be an efficie...
HOST
2008
IEEE
14 years 2 months ago
2008
IEEE
—Masking is a side-channel countermeasure that randomizes side-channel leakage, such as the power dissipation of a circuit. Masking is only effective on the condition that the in...