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MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
14 years 2 months ago
Scalable Cache Miss Handling for High Memory-Level Parallelism
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
James Tuck, Luis Ceze, Josep Torrellas
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
14 years 1 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
SIGOPSE
1998
ACM
14 years 25 days ago
MMLite: a highly componentized system architecture
MMLite is a modular system architecture that is suitable for a wide variety of hardware and applications. The system provides a selection of object-based components that are dynam...
Johannes Helander, Alessandro Forin
MSS
2003
IEEE
108views Hardware» more  MSS 2003»
14 years 1 months ago
Effective Management of Hierarchical Storage Using Two Levels of Data Clustering
When data resides on tertiary storage, clustering is the key to achieving high retrieval performance. However, a straightforward approach to clustering massive amounts of data on ...
Ratko Orlandic
DAC
2008
ACM
14 years 9 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada