652 search results - page 43 / 131 » Time Management in The High Level Architecture |
LSSC
2005
Springer
14 years 2 months ago
2005
Springer
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adap...
CORR
2006
Springer
13 years 8 months ago
2006
Springer
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
WMPI
2004
ACM
14 years 2 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
MMS
2002
13 years 8 months ago
2002
This paper offers a high-level retrospective overview of the GOPI middleware platform which is the outcome of a three year project aimed at the development of generic, configurabl...
ICPADS
2006
IEEE
14 years 2 months ago
2006
IEEE
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...