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» Time Management in The High Level Architecture
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GLVLSI
2007
IEEE
211views VLSI» more  GLVLSI 2007»
14 years 3 months ago
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
Salvatore Carta, Andrea Acquaviva, Pablo Garcia De...
ISLPED
2004
ACM
157views Hardware» more  ISLPED 2004»
14 years 2 months ago
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cell...
Stefanos Kaxiras, Polychronis Xekalakis
TC
2008
13 years 8 months ago
Exploiting In-Memory and On-Disk Redundancy to Conserve Energy in Storage Systems
Abstract--Today's storage systems place an imperative demand on energy efficiency. A storage system often places single-rotationrate disks into standby mode by stopping them f...
Jun Wang, Xiaoyu Yao, Huijun Zhu
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
14 years 1 months ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
ICSOC
2004
Springer
14 years 2 months ago
Knowledge-driven interactions with services across ad hoc networks
Service oriented computing, with its aim of unhindered interoperability, is an appropriate paradigm for ad hoc networks, which are characterized by physical mobility of heterogeno...
Rohan Sen, Radu Handorean, Gruia-Catalin Roman, Gr...