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VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
14 years 11 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
14 years 2 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
CIDR
2011
266views Algorithms» more  CIDR 2011»
13 years 2 months ago
Consistency in a Stream Warehouse
A stream warehouse is a Data Stream Management System (DSMS) that stores a very long history, e.g. years or decades; or equivalently a data warehouse that is continuously loaded. ...
Lukasz Golab, Theodore Johnson
HICSS
1998
IEEE
142views Biometrics» more  HICSS 1998»
14 years 3 months ago
Meetings in a Virtual Space: Creating a Digital Document
Improvements in computer network infrastructures and information utilities have led to an increase in the number of social and work interactions carried out `virtually' by ge...
Lori Toomey, Lia Adams, Elizabeth F. Churchill
ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
14 years 2 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...