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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 4 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
FPL
2005
Springer
111views Hardware» more  FPL 2005»
14 years 28 days ago
Mutable Codesign for Embedded Protocol Processing
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
Todd S. Sproull, Gordon J. Brebner, Christopher E....
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
14 years 7 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
RTCSA
2005
IEEE
14 years 1 months ago
LyraNET: A Zero-Copy TCP/IP Protocol Stack for Embedded Operating Systems
Embedded systems are usually resource limited in terms of processing power, memory, and power consumption, thus embedded TCP/IP should be designed to make the best use of limited ...
Yun-Chen Li, Mei-Ling Chiang
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 2 months ago
Model-based synthesis and optimization of static multi-rate image processing algorithms
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
Joachim Keinert, Hritam Dutta, Frank Hannig, Chris...