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ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 8 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
IPPS
2006
IEEE
14 years 2 months ago
Online strategies for high-performance power-aware thread execution on emerging multiprocessors
Granularity control is an effective means for trading power consumption with performance on dense shared memory multiprocessors, such as multi-SMT and multi-CMP systems. In this p...
Matthew Curtis-Maury, James Dzierwa, Christos D. A...
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
14 years 26 days ago
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
Gernot Koch, Taewhan Kim, Reiner Genevriere
SIGOPSE
1998
ACM
14 years 20 days ago
MMLite: a highly componentized system architecture
MMLite is a modular system architecture that is suitable for a wide variety of hardware and applications. The system provides a selection of object-based components that are dynam...
Johannes Helander, Alessandro Forin
HOTI
2005
IEEE
14 years 2 months ago
Long Round-Trip Time Support with Shared-Memory Crosspoint Buffered Packet Switch
— The amount of memory in buffered crossbars in combined input-crosspoint buffered switches is proportional to the number of crosspoints, or O(N2 ), where N is the number of port...
Ziqian Dong, Roberto Rojas-Cessa