70 search results - page 10 / 14 » Time-Energy Design Space Exploration for Multi-Layer Memory ... |
DAC
2000
ACM
14 years 8 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
SAMOS
2005
Springer
14 years 16 days ago
2005
Springer
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
LCTRTS
2004
Springer
14 years 12 days ago
2004
Springer
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
MICRO
2009
IEEE
14 years 1 months ago
2009
IEEE
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
ERSA
2010
13 years 5 months ago
2010
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...