769 search results - page 100 / 154 » Timed Circuit Synthesis Using Implicit Methods |
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with ...
FPGA
1999
ACM
14 years 2 months ago
1999
ACM
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
RT
2004
Springer
14 years 3 months ago
2004
Springer
Falling snow has the visual property that it is simultaneously a set of discrete moving particles as well as a dynamic texture. To capture the dynamic texture properties of fallin...
TCAD
2002
13 years 9 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
ICCAD
1995
IEEE
14 years 1 months ago
1995
IEEE
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...