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» Timed Circuit Synthesis Using Implicit Methods
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ANSS
2000
IEEE
14 years 4 days ago
Multi-Resolution Modeling of Power Converter Using Waveform Reconstruction
Computer simulation of switching power converters is complicated by the discontinuous (switching) nature of the converter waveforms. When switching details of the waveforms are of...
Yuwei Luo, Roger Dougal, Enrico Santi
ICCAD
1999
IEEE
109views Hardware» more  ICCAD 1999»
14 years 1 days ago
Transient sensitivity computation for transistor level analysis and tuning
This paper presents a general method for computing transient sensitivities using both the direct and adjoint methods in event driven controlled explicit simulation algorithms that...
Tuyen V. Nguyen, Peter O'Brien, David W. Winston
EUROGP
2000
Springer
116views Optimization» more  EUROGP 2000»
13 years 11 months ago
An Extrinsic Function-Level Evolvable Hardware Approach
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...
Tatiana Kalganova
DAC
2001
ACM
14 years 8 months ago
An Algorithm for Bi-Decomposition of Logic Functions
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal ...
Alan Mishchenko, Bernd Steinbach, Marek A. Perkows...
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
12 years 3 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang