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» Timed Circuit Synthesis Using Implicit Methods
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ICCAD
2004
IEEE
150views Hardware» more  ICCAD 2004»
14 years 4 months ago
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
Maxim Teslenko, Elena Dubrova
ECCV
2004
Springer
14 years 9 months ago
Hand Motion from 3D Point Trajectories and a Smooth Surface Model
A method is proposed to track the full hand motion from 3D points reconstructed using a stereoscopic set of cameras. This approach combines the advantages of methods that use 2D mo...
Guillaume Dewaele, Frederic Devernay, Radu Horaud
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
13 years 12 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
DAC
1994
ACM
13 years 11 months ago
Exact Minimum Cycle Times for Finite State Machines
In current research, the minimum cycle times of finite state machines are estimated by computing the delays of the combinational logic in the finite state machines. Even though th...
William K. C. Lam, Robert K. Brayton, Alberto L. S...
RTSS
2006
IEEE
14 years 1 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...