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» Timed Circuit Synthesis Using Implicit Methods
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ICCAD
1993
IEEE
104views Hardware» more  ICCAD 1993»
13 years 11 months ago
Parallel timing simulation on a distributed memory multiprocessor
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
Chih-Po Wen, Katherine A. Yelick
TCAD
1998
107views more  TCAD 1998»
13 years 7 months ago
Optimizing dominant time constant in RC circuits
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El ...
TCAD
2008
102views more  TCAD 2008»
13 years 7 months ago
Quantum Circuit Simplification and Level Compaction
Abstract--Quantum circuits are time-dependent diagrams describing the process of quantum computation. Usually, a quantum algorithm must be mapped into a quantum circuit. Optimal sy...
Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller...
ICCAD
2009
IEEE
119views Hardware» more  ICCAD 2009»
13 years 5 months ago
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
ASPDAC
2009
ACM
122views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Tolerating process variations in high-level synthesis using transparent latches
—Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
Yibo Chen, Yuan Xie