769 search results - page 29 / 154 » Timed Circuit Synthesis Using Implicit Methods |
ASYNC
2005
IEEE
14 years 4 months ago
2005
IEEE
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
Publication
A large class of systems of biological and technological relevance can be described as analog networks, that is, collections of dynamic devices interconnected by links of varying s...
VLSID
2009
IEEE
14 years 11 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
ISQED
2005
IEEE
14 years 4 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
FM
1999
Springer
14 years 2 months ago
1999
Springer
We present novel techniques for efficient controller synthesis for untimed and timed systems with respect to invariance and reachability properties. In the untimed case, we give al...