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» Timed Circuit Synthesis Using Implicit Methods
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ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
14 years 4 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
FORMATS
2003
Springer
14 years 3 months ago
On Timing Analysis of Combinational Circuits
In this paper we report some progress in applying timed automata technology to large-scale problems. We focus on the problem of finding maximal stabilization time for combinationa...
Ramzi Ben Salah, Marius Bozga, Oded Maler
ASPDAC
2005
ACM
101views Hardware» more  ASPDAC 2005»
14 years 10 days ago
A wideband hierarchical circuit reduction for massively coupled interconnects
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
APN
2007
Springer
14 years 4 months ago
A Compositional Method for the Synthesis of Asynchronous Communication Mechanisms
Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed concurrent processes. In previous work, an automatic ...
Kyller Costa Gorgônio, Jordi Cortadella, Fei...
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
14 years 5 months ago
Debugging of Toffoli networks
—Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible lo...
Robert Wille, Daniel Große, Stefan Frehse, G...