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» Timed Circuit Synthesis Using Implicit Methods
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ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
14 years 3 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
14 years 4 months ago
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
GLVLSI
2000
IEEE
105views VLSI» more  GLVLSI 2000»
14 years 2 months ago
An evolutionary approach to timing driven FPGA placement
: We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the...
R. Venkatraman, Lalit M. Patnaik
SIGGRAPH
1998
ACM
14 years 2 months ago
Large Steps in Cloth Simulation
The bottle-neck in most cloth simulation systems is that time steps must be small to avoid numerical instability. This paper describes a cloth simulation system that can stably ta...
David Baraff, Andrew P. Witkin
CHES
2011
Springer
276views Cryptology» more  CHES 2011»
12 years 10 months ago
FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control
Abstract. The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Meta...
Mehrdad Majzoobi, Farinaz Koushanfar, Srinivas Dev...