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ETS
2006
IEEE
113views Hardware» more  ETS 2006»
14 years 4 months ago
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
Alexandre M. Amory, Kees Goossens, Erik Jan Marini...
SODA
2010
ACM
133views Algorithms» more  SODA 2010»
14 years 7 months ago
Testing additive integrality gaps
We consider the problem of testing whether the maximum additive integrality gap of a family of integer programs in standard form is bounded by a given constant. This can be viewed...
Friedrich Eisenbrand, Nicolai Hähnle, Dömötör ...
ITC
2003
IEEE
124views Hardware» more  ITC 2003»
14 years 3 months ago
Power-aware NoC Reuse on the Testing of Core-based Systems
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously prop...
Érika F. Cota, Luigi Carro, Flávio R...
GLOBECOM
2008
IEEE
14 years 4 months ago
Using Higher Order Cyclostationarity to Identify Space-Time Block Codes
—Research in cognitive radios has renewed interest in tools, such as spectrum estimation and modulation identification, to characterize the radio frequency (RF) environment. The...
Marcus R. DeYoung, Robert W. Heath Jr., Brian L. E...