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COMPSAC
2004
IEEE
13 years 11 months ago
Mutation-Based Testing Criteria for Timeliness
Temporal correctness is crucial to the dependability of real-time systems. Few methods exist to test for temporal correctness and most existing methods are ad-hoc. A problem with ...
Robert Nilsson, Jeff Offutt, Sten F. Andler
ETS
2010
IEEE
174views Hardware» more  ETS 2010»
13 years 8 months ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
ATS
2004
IEEE
108views Hardware» more  ATS 2004»
13 years 11 months ago
Rapid and Energy-Efficient Testing for Embedded Cores
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman ...
ITC
1998
IEEE
61views Hardware» more  ITC 1998»
13 years 11 months ago
Test session oriented built-in self-testable data path synthesis
Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design spa...
Han Bin Kim, Takeshi Takahashi, Dong Sam Ha
NIPS
2007
13 years 9 months ago
Sequential Hypothesis Testing under Stochastic Deadlines
Most models of decision-making in neuroscience assume an infinite horizon, which yields an optimal solution that integrates evidence up to a fixed decision threshold; however, u...
Peter Frazier, Angela Yu