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EURODAC
1990
IEEE
92views VHDL» more  EURODAC 1990»
13 years 11 months ago
Accelerated test pattern generation by cone-oriented circuit partitioning
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
Torsten Grüning, Udo Mahlstedt, Wilfried Daeh...
STACS
2000
Springer
13 years 11 months ago
The Complexity of Planarity Testing
We clarify the computational complexity of planarity testing, by showing that planarity testing is hard for L, and lies in SL. This nearly settles the question, since it is widely...
Eric Allender, Meena Mahajan
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
13 years 10 months ago
Defect aware X-filling for low-power scan testing
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
S. Balatsouka, V. Tenentes, Xrysovalantis Kavousia...
PTS
1998
81views Hardware» more  PTS 1998»
13 years 9 months ago
Testing Temporal Logic Properties in Distributed Systems
Based on the notion of event-based behavioral abstraction EBBA we specify properties of object-oriented distributed systems in linear time temporal logic. These properties are the...
Falk Dietrich, Xavier Logean, Shawn Koppenhoefer, ...
INTEGRATION
2006
102views more  INTEGRATION 2006»
13 years 7 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...