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DATE
1998
IEEE
106views Hardware» more  DATE 1998»
13 years 12 months ago
March Tests for Word-Oriented Memories
Most memory test algorithms are optimized tests for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e....
A. J. van de Goor, Issam B. S. Tlili
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 12 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
DBSEC
2008
137views Database» more  DBSEC 2008»
13 years 9 months ago
Towards Automation of Testing High-Level Security Properties
Abstract. Many security problems only become apparent after software is deployed, and in many cases a failure has occurred prior to the awareness of the problem. Although many woul...
Aiman Hanna, Hai Zhou Ling, Jason Furlong, Mourad ...
ICSE
2012
IEEE-ACM
11 years 10 months ago
make test-zesti: A symbolic execution solution for improving regression testing
Abstract—Software testing is an expensive and time consuming process, often involving the manual creation of comprehensive regression test suites. However, current testing method...
Paul Dan Marinescu, Cristian Cadar
ITC
1997
IEEE
123views Hardware» more  ITC 1997»
13 years 12 months ago
Modifying User-Defined Logic for Test Access to Embedded Cores
Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (ZJDL) surrounding the core may restrict the set of test vectors that can be a...
Bahram Pouya, Nur A. Touba