176 search results - page 26 / 36 » Timed Verification of Asynchronous Circuits |
COMCOM
2000
13 years 7 months ago
2000
This paper is devoted to the presentation of the RT-LOTOS formal description technique, which is a formalism suited for applications where concurrency, complex synchronization pat...
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
With the scaling of technology, power grid noise is becoming increasingly significant for circuit performance. A typical power grid circuit contains millions of linear elements, m...
FPL
1999
Springer
13 years 12 months ago
1999
Springer
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
NOCS
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...