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» Timing Analysis of Embedded Software for Speculative Process...
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DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 3 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
JILP
2000
90views more  JILP 2000»
13 years 8 months ago
Speculative Updates of Local and Global Branch History: A Quantitative Analysis
In today's wide-issue processors, even small branch-misprediction rates introduce substantial performance penalties. Worse yet, inadequate branch prediction creates a bottlen...
Kevin Skadron, Margaret Martonosi, Douglas W. Clar...
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 6 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
ICISC
2009
132views Cryptology» more  ICISC 2009»
13 years 6 months ago
Side-Channel Analysis of Cryptographic Software via Early-Terminating Multiplications
Abstract. The design of embedded processors demands a careful tradeoff between many conflicting objectives such as performance, silicon area and power consumption. Finding such a t...
Johann Großschädl, Elisabeth Oswald, Da...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 2 months ago
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
— Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in “trusted” software t...
Divya Arora, Srivaths Ravi, Anand Raghunathan, Nir...