Sciweavers

758 search results - page 125 / 152
» Timing Analysis of Optimised Code
Sort
View
CODES
2007
IEEE
14 years 2 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
CODES
2006
IEEE
14 years 1 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
MICRO
2006
IEEE
124views Hardware» more  MICRO 2006»
14 years 1 months ago
LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks
Computer security is severely threatened by software vulnerabilities. Prior work shows that information flow tracking (also referred to as taint analysis) is a promising techniqu...
Feng Qin, Cheng Wang, Zhenmin Li, Ho-Seop Kim, Yua...
STOC
2000
ACM
174views Algorithms» more  STOC 2000»
14 years 12 hour ago
Noise-tolerant learning, the parity problem, and the statistical query model
We describe a slightly subexponential time algorithm for learning parity functions in the presence of random classification noise, a problem closely related to several cryptograph...
Avrim Blum, Adam Kalai, Hal Wasserman
ENTCS
2006
112views more  ENTCS 2006»
13 years 7 months ago
A Petri-Net Based Reflective Framework for the Evolution of Dynamic Systems
Nowadays, software evolution is a very hot topic. Many applications need to be updated or extended with new characteristics during their lifecycle. Software evolution is character...
Lorenzo Capra, Walter Cazzola