40 search results - page 3 / 8 » Timing Driven Placement for Large Standard Cell Circuits |
143
click to vote
DAC
2006
ACM
16 years 6 months ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
166
click to vote
ISPD
1997
ACM
15 years 9 months ago
1997
ACM
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
134
click to vote
ARITH
1999
IEEE
15 years 10 months ago
1999
IEEE
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
155
click to vote
ISPD
2005
ACM
15 years 11 months ago
2005
ACM
In this paper, we develop a mixed-size placement tool, Dragon2005, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partition...
156
click to vote
ASPDAC
2008
ACM
15 years 7 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...