483 search results - page 47 / 97 » Timing Games and Shared Memory |
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
ICCD
1994
IEEE
14 years 2 months ago
1994
IEEE
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in sharedmemory multiprocessors. These directories use specialpurpose caches of poin...
MICRO
2006
IEEE
14 years 3 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
ICALP
1994
Springer
14 years 2 months ago
1994
Springer
We introduce a formal framework to study the time and space complexity of computing with faulty memory. For the fault-free case, time and space complexities were studied using the...
HPCA
1996
IEEE
14 years 2 months ago
1996
IEEE
This paper compares several implementations of entry consistency (EC) and lazy release consistency (LRC), two relaxed memory models in use with software distributed shared memory ...