72 search results - page 5 / 15 » Timing Optimization of Logic Network Using Gate Duplication |
IJCNN
2006
IEEE
14 years 1 months ago
2006
IEEE
—This paper presents the design of an optimal Auxiliary Transient Neurocontroller (ATNC) for the Gate Controlled Series Capacitor (GCSC) in a multi-machine power system. GCSC is ...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
GECCO
2006
Springer
13 years 11 months ago
2006
Springer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...