290 search results - page 13 / 58 » Timing analysis in high-level synthesis |
ICCD
1993
IEEE
13 years 12 months ago
1993
IEEE
DAC
2006
ACM
14 years 8 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
FPL
2003
Springer
14 years 28 days ago
2003
Springer
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
TCAD
2008
13 years 7 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...