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» Timing analysis in high-level synthesis
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INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 7 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 8 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
IPPS
2009
IEEE
14 years 2 months ago
High-level estimation and trade-off analysis for adaptive real-time systems
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...
Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrho...
IASTEDSE
2004
13 years 9 months ago
Mapping UML statecharts to java code
The Unified Modeling Language (UML) statechart diagram is used for modeling the dynamic aspects of systems. The UML statechart diagrams include many concepts that are not present ...
Iftikhar Azim Niaz, Jiro Tanaka
JMIV
2007
122views more  JMIV 2007»
13 years 7 months ago
Fast Image Inpainting Based on Coherence Transport
High-quality image inpainting methods based on nonlinear higher-order partial differential equations have been developed in the last few years. These methods are iterative by natur...
Folkmar Bornemann, Tom März