As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Abstract--In this paper, the problem of bus driven floorplanning is addressed. Given a set of modules and bus specifications, a floorplan solution including the bus routes will be ...
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
—We propose a new multi-hop routing protocol for wireless sensor networks, suited for monitoring and control applications. The aim of this research is to adapt flat and hierarch...
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...