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» Timing driven maze routing
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ISPD
1998
ACM
244views Hardware» more  ISPD 1998»
14 years 1 months ago
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Tilmann Stöhr, Markus Alt, Asmus Hetzel, J&uu...
ASPDAC
2008
ACM
109views Hardware» more  ASPDAC 2008»
13 years 11 months ago
TCG-based multi-bend bus driven floorplanning
Abstract--In this paper, the problem of bus driven floorplanning is addressed. Given a set of modules and bus specifications, a floorplan solution including the bus routes will be ...
Tilen Ma, Evangeline F. Y. Young
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
14 years 2 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
CONIELECOMP
2011
IEEE
13 years 23 days ago
DSRP: Distributed SensorWeb Routing Protocol
—We propose a new multi-hop routing protocol for wireless sensor networks, suited for monitoring and control applications. The aim of this research is to adapt flat and hierarch...
Abhinav Valada, David Kohanbash, George Kantor
ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
14 years 1 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...