This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishn...
In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations a...
Guenter Stenz, Bernhard M. Riess, Bernhard Rohflei...
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...