264 search results - page 10 / 53 » Timing driven power gating |
DATE
1998
IEEE
14 years 26 days ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
ISPD
1997
ACM
14 years 24 days ago
1997
ACM
In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations a...
ISCAS
2008
IEEE
14 years 3 months ago
2008
IEEE
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
ICCAD
1994
IEEE
14 years 22 days ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...