264 search results - page 36 / 53 » Timing driven power gating |
FPGA
2010
ACM
14 years 5 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transf...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
JAIR
2010
13 years 7 months ago
2010
Because an agent’s resources dictate what actions it can possibly take, it should plan which resources it holds over time carefully, considering its inherent limitations (such a...