264 search results - page 45 / 53 » Timing driven power gating |
ISQED
2009
IEEE
14 years 3 months ago
2009
IEEE
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
DATE
2009
IEEE
14 years 15 days ago
2009
IEEE
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...
ASYNC
2002
IEEE
14 years 1 months ago
2002
IEEE
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
ASPDAC
2009
ACM
14 years 3 months ago
2009
ACM
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...