57 search results - page 7 / 12 » Timing metrics for physical design of deep submicron technol... |
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
ISPD
1998
ACM
13 years 11 months ago
1998
ACM
This paper describes an important new facility for timing-driven design applications within the new CHDStd standard for a SEMATECH design system for large complex chips. We first ...
SEMWEB
2010
Springer
13 years 5 months ago
2010
Springer
As knowledge bases move into the landscape of larger ontologies and have terabytes of related data, we must work on optimizing the performance of our tools. We are easily tempted t...
ISQED
2011
IEEE
12 years 11 months ago
2011
IEEE
As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors...