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» Timing model reduction for hierarchical timing analysis
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ICCAD
2008
IEEE
223views Hardware» more  ICCAD 2008»
14 years 5 months ago
Decoupling capacitance allocation for timing with statistical noise model and timing analysis
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
Takashi Enami, Masanori Hashimoto, Takashi Sato
ISQED
2005
IEEE
92views Hardware» more  ISQED 2005»
14 years 2 months ago
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis
This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the...
Chung-Kuan Tsai, Malgorzata Marek-Sadowska
DAC
2009
ACM
14 years 25 days ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen
ASPDAC
2005
ACM
122views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Block based statistical timing analysis with extended canonical timing model
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
14 years 5 months ago
A flexibility aware budgeting for hierarchical flow timing closure
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
Olivier Omedes, Michel Robert, Mohammed Ramdani