4164 search results - page 43 / 833 » Timing model reduction for hierarchical timing analysis |
DAC
2008
ACM
14 years 10 months ago
2008
ACM
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
CONCUR
2010
Springer
13 years 10 months ago
2010
Springer
Abstract. In this paper we introduce a real-time extension of the concurrent object modeling language Creol which is based on duration statements indicating best and worst case exe...
JSW
2008
13 years 9 months ago
2008
Precise analysis of the Web structure can facilitate data pre-processing and enhance the accuracy of the mining results in the procedure of Web usage mining. STPN Stochastic Timed...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
A technique based on the sensitivity of the output to input waveform is presented for accurate propagation of delay information through a gate for the purpose of static timing ana...
JPDC
2011
13 years 4 months ago
2011
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource ...