93 search results - page 4 / 19 » Timing optimization of FPGA placements by logic replication |
CCGRID
2007
IEEE
14 years 4 months ago
2007
IEEE
Data replication is an excellent technique to move and cache data close to users. By replication, data access performance can be improved dramatically. One of the challenges in da...
ICCTA
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we propose a placement method for islandstyle FPGAs, based on fast yet very good initial placement followed by refinement using ultra-low temperature Simulated Anne...
ICCAD
2001
IEEE
14 years 6 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
FPGA
1998
ACM
14 years 2 months ago
1998
ACM
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
FPGA
1998
ACM
14 years 2 months ago
1998
ACM
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA...