51 search results - page 5 / 11 » Timing variation-aware high-level synthesis |
DAC
2012
ACM
11 years 9 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
CORR
2006
Springer
13 years 7 months ago
2006
Springer
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
FPL
2009
Springer
13 years 11 months ago
2009
Springer
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
GW
2005
Springer
14 years 27 days ago
2005
Springer
Abstract. The work described in this abstract presents a roadmap towards the creation and specification of a virtual humanoid capable of performing expressive gestures in real tim...