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RTAS
2008
IEEE
14 years 3 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
ARC
2006
Springer
124views Hardware» more  ARC 2006»
14 years 11 days ago
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
Su-Shin Ang, George A. Constantinides, Peter Y. K....
CVPR
2005
IEEE
14 years 10 months ago
The Modified pbM-Estimator Method and a Runtime Analysis Technique for the RANSAC Family
Robust regression techniques are used today in many computer vision algorithms. Chen and Meer recently presented a new robust regression technique named the projection based M-est...
Stas Rozenfeld, Ilan Shimshoni
HPCA
2003
IEEE
14 years 9 months ago
A Statistically Rigorous Approach for Improving Simulation Methodology
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
Joshua J. Yi, David J. Lilja, Douglas M. Hawkins
DAC
2007
ACM
14 years 9 months ago
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhamm...