188 search results - page 23 / 38 » Timing-driven optimization using lookahead logic circuits |
PADS
1996
ACM
14 years 2 months ago
1996
ACM
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend th...
IOLTS
2008
IEEE
14 years 4 months ago
2008
IEEE
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
ARVLSI
2001
IEEE
14 years 1 months ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
DATE
2009
IEEE
14 years 5 months ago
2009
IEEE
—Redundancy Addition and Removal (RAR) is a restructuring technique used in the synthesis and optimization of logic designs. It can remove an existing target wire and add an alte...
SASP
2009
IEEE
14 years 5 months ago
2009
IEEE
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...