188 search results - page 24 / 38 » Timing-driven optimization using lookahead logic circuits |
DAC
2001
ACM
14 years 11 months ago
2001
ACM
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...
ISQED
2005
IEEE
14 years 3 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
ISVLSI
2007
IEEE
14 years 4 months ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
VLSID
2002
IEEE
14 years 3 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
CEC
2011
IEEE
12 years 10 months ago
2011
IEEE
—Constrained Genetic Programming (CGP) is a method of searching the Genetic Programming search space non-uniformly, giving preferences to certain subspaces according to some heur...