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» Timing-driven placement for FPGAs
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IPPS
2006
IEEE
14 years 1 months ago
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
The development of Field Programmable Gate Arrays (FPGAs) had tremendous improvements in the last few years. They were extended from simple logic circuits to complex Systems-on-Ch...
Michael Hübner, Christian Schuck, Jürgen...
FPGA
1995
ACM
149views FPGA» more  FPGA 1995»
13 years 11 months ago
PathFinder: A Negotiation-based Performance-driven Router for FPGAs
Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused...
Larry McMurchie, Carl Ebeling
FPL
2010
Springer
124views Hardware» more  FPL 2010»
13 years 5 months ago
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
Farnaz Gharibian, Lesley Shannon, Peter Jamieson
ERSA
2010
152views Hardware» more  ERSA 2010»
13 years 5 months ago
Persistent CAD for in-the-field Power Optimization
A major focus within the Integrated Chip (IC) industry is reducing power consumption of devices. In this paper, we explore the idea of persistent CAD algorithms that constantly imp...
Peter Jamieson
FPGA
2003
ACM
154views FPGA» more  FPGA 2003»
14 years 28 days ago
Parallel placement for field-programmable gate arrays
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
Pak K. Chan, Martine D. F. Schlag