134 search results - page 20 / 27 » Tolerance Models in Hardware Description Languages |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
DOLAP
2010
ACM
13 years 5 months ago
2010
ACM
Relational database systems have been the dominating technology to manage and analyze large data warehouses. Moreover, the ER model, the standard in database design, has a close r...
ASPDAC
2008
ACM
13 years 8 months ago
2008
ACM
—In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We a multiplier description language which abstracts from low-leve...
CAV
2005
Springer
14 years 1 months ago
2005
Springer
Model checking has proven to be an effective technology for verification and debugging in hardware and more recently in software domains. We believe that recent trends in both th...