48 search results - page 4 / 10 » Tolerating data access latency with register preloading |
EMSOFT
2005
Springer
14 years 16 days ago
2005
Springer
With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely ...
MICRO
2000
IEEE
13 years 6 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
SC
2009
ACM
14 years 1 months ago
2009
ACM
Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. We introduce a hardware technique called “di...
HPCA
2011
IEEE
12 years 10 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
D-NUCA L2 caches are able to tolerate the increasing wire delay effects due to technology scaling thanks to their banked organization, broadcast line search and data promotion/dem...