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» Topological Design of Interconnected LAN-MAN Networks
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ASAP
2003
IEEE
108views Hardware» more  ASAP 2003»
14 years 26 days ago
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
Terry Tao Ye, Giovanni De Micheli
CODES
2003
IEEE
14 years 26 days ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
IMC
2010
ACM
13 years 5 months ago
On the impact of layer-2 on node degree distribution
The Internet topology data collected through traceroute exploration has been extensively studied in the past. In particular, a remarkable property of the Internet, the power-law s...
Pascal Mérindol, Benoit Donnet, Olivier Bon...
GECCO
2009
Springer
148views Optimization» more  GECCO 2009»
14 years 2 months ago
Evolutionary optimization of multistage interconnection networks performance
The paper deals with optimization of collective communications on multistage interconnection networks (MINs). In the experimental work, unidirectional MINs like Omega, Butterfly a...
Jirí Jaros
JCP
2008
162views more  JCP 2008»
13 years 7 months ago
A Hypercube-based Scalable Interconnection Network for Massively Parallel Computing
An important issues in the design of interconnection networks for massively parallel computers is scalability. A new scalable interconnection network topology, called Double-Loop H...
Youyao Liu, Jungang Han, Huimin Du